1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming a semiconductor device with a gate spacer.
2. Description of Related Arts
In general, a dynamic random access memory device (DRAM) is classified into a cell region and a peripheral region. Transistors formed in the peripheral region adopt sources/drains having a lightly doped drain (LDD) structure. Particularly, a gate spacer is employed to form the sources/drains having the LDD structure.
FIGS. 1A and 1B are cross-sectional views for illustrating a method for fabricating a conventional semiconductor device.
Referring to FIG. 1A, a field oxide layer 12 for device isolation is formed in predetermined regions of a substrate 11 divided into a dense (D) region where gate structures are densely disposed and a loose (L) region where gate structures are loosely disposed. Afterwards, a plurality of gate structures 13 are formed on the substrate 11. At this time, although not illustrated, each of the gate structures 13 includes a gate insulation layer, a gate electrode and a gate hard mask.
Next, impurities in low concentration are implanted to form a plurality of LDD junctions 14 in predetermined regions of the substrate 11 corresponding to lateral sides of the individual gate structures 13. Then, a buffer oxide layer 15, a spacer nitride layer 16 and a spacer oxide layer 17 are sequentially formed on the above obtained substrate structure.
Referring to FIG. 1B, a mask 18 for forming a heavily doped P-type or N-type sources/drains is formed on the spacer oxide layer 17. Thereafter, an etching process for forming spacers is carried out to form a plurality of gate spacers 100 on sidewalls of the gate structure 13. At this time, each of the gate spacers 100 includes a patterned buffer oxide layer 15A, a patterned spacer nitride layer 16A and a patterned spacer oxide layer 17A.
The aforementioned etching process for forming the gate spacers 100 is performed under a condition of a low pressure and a small amount of gas flow. Especially, the low pressure ranges from 50 mtorr to 100 mtorr, and the gas flow ranges from 50 sccm to 100 sccm. For instance, the etching process for forming the gate spacers 100 proceeds by employing a fluorine-based gas such as CF4 gas as a main etch gas and oxygen (O2) and argon (Ar) as assisting etch gases. At this time, a total amount of gas flow of CF4/O2/Ar is in a range from 50 sccm to 100 sccm, and a chamber pressure is maintained in low pressure ranging from 50 mtorr to 100 mtorr. Through this etching process, each of the gate spacers 100 has rounded edges.
However, as a semiconductor device has been scaled down, sizes of gate structures and spacing distances between the gate structures become inconsistent because materials used for forming spacers have a poor step-coverage characteristic and etch recipes that are not applied uniformly.
As a result of the differentiated sizes and spacing distances between the gate structures, widths of the spacers become different. This difference causes a threshold voltage to vary in a peripheral region, thereby further resulting in degradation of device margins.
The detailed explanation on adverse effects of the differentiated sizes and spacing distances between the gate structures will be provided with reference to the table in below.
TABLE 1D regionL regionFirst line width of a gate structure (F1)0.1990.184Second line width of a resulting structure after0.3320.321depositing a spacer material (F2)Third line width of a resulting structure after0.3280.318etching the spacer material (F3)(F2 − F1)/20.0670.068(F3 − F1)/20.0650.067
As shown in Table 1, the first line width F1 of the gate structure is smaller in the L region where the spacing distance between the gate structures is wide than in the D region where the spacing distance between the gate structures is narrow.
In consideration of the difference in the first line widths F1 of the gate structures and on the basis of the second line widths F2 of the gate structures after the deposition of the spacer material, for instance, an oxide layer, the spacer material is more thinly deposited as the spacing distance between the gate structures is narrow. For example, the second line width F2 of the gate structure after the deposition of the spacer material in the D region is 0.332, meaning that the second line width F2 increases by 0.133. On the other hand, the second line width F2 of the gate structure in the L region is 0.321, meaning that the second line width F2 increases by 0.137. Based on this fact, it is verified that the spacer material is deposited more thickly in the L region than in the D region.
Also, after the spacer material is etched, the third line width F3 in the D region is 0.328, while the third line width F3 in the L region is 0.318. These different third line widths F3 indicate that the spacer material is etched more in the D region than in the L region.
On the basis of Table 1, the total thickness of the spacer in the L region is greater than in the D region by 40 Å, corresponding to 40 mV of a threshold voltage of a transistor in a peripheral region. In consideration of a range of the threshold voltage of the transistor in the peripheral region in a 120 nm semiconductor technology, i.e., 150 mV, this value of 40 mV is a very high variation in the threshold voltage.